1. Field of the Invention
Generally, the present disclosure relates to microstructure devices, such as integrated circuits, and, more particularly, to the techniques for dicing substrates so as to provide the individual devices.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable base materials for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like. The individual integrated circuits are arranged in an array on the wafer, wherein most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the semiconductor substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In an attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with low-k dielectric materials, has become a frequently used alternative in the formation of so-called interconnect structures, comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
In sophisticated semiconductor devices, the continuous shrinkage of the critical dimensions of transistors, and thus of metal features, not only provides superior performance with respect to operating speed but also results in a significant increased power consumption, thereby requiring superior heat dissipation capabilities of the semiconductor devices and the corresponding package substrates. Typically, the metallization system of the semiconductor device is formed in close proximity to the semiconductor-based circuit elements, such as fast switching transistors and the like, and provides, in addition to the electrical contact to the semiconductor-based circuit elements, also an efficient thermally conductive path in order to dissipate the waste heat created within the device level into the metallization system and finally to the package substrate, which in turn may be connected to an external heatsink, if required. Due to the increasing complexity of the metallization system in sophisticated semiconductor devices, however, the number of stacked metallization layers may have to be increased, while at the same time sophisticated dielectric materials, such as low-k dielectric materials and ultra low-k (ULK) materials, are increasingly used in order to reduce the parasitic capacitance, thereby improving the overall electrical performance. On the other hand, the thermal performance, i.e., the heat dissipation capability, of such complex metallization systems may be significantly reduced since typically the low-k dielectric materials and the ULK materials have a significantly reduced heat conductivity compared to conventional dielectric materials, such as silicon dioxide, silicon nitride and the like. Thus, the thermal resistance of complex metallization systems may increase, while at the same time the amount of waste heat created in the device level, i.e., in the semiconductor-based circuit elements, may also increase, thereby requiring additional heat dissipation capabilities in complex semiconductor devices. To this end, frequently the substrate material of the semiconductor device, typically provided in the form of a silicon material, may be used for transferring heat to the periphery of the semiconductor device. That is, the substrate material may have a moderately high thermal conductivity and is also in close proximity to the heat-producing semiconductor circuit elements, so that an efficient heat dissipation path is established from the active semiconductor material into the depth of the substrate. For this reason, frequently the rear side or back side of the substrate may receive an appropriate heat transfer material so as to efficiently connect to the package substrate, wherein well-established metal-based materials, such as indium and the like, are used as a thermal interfacial material due to superior heat conductivity. In other cases, gallium, silver, copper and the like may also be efficiently used as thermal interfacial materials. Due to the material characteristics, such as diffusion behavior, adhesion to specific materials, such as silicon and the like, the thermal interfacial material is typically not directly formed on the substrate back side but requires additional material layers in order to obtain the desired thermal, mechanical or chemical behavior for the coupling between the substrate back side and a package. For this purpose, an adhesion layer is frequently formed on the surface of the substrate back side in order to provide adhesion of the following materials to the semiconductor material of the substrate. For instance, aluminum, aluminum alloys, titanium, titanium nitride, tantalum, tantalum nitride and tantalum silicide are materials that are frequently used as an adhesion material. Thereafter, a barrier material, such as titanium, tantalum, tantalum nitride, tantalum silicide, nickel, chromium and the like, is provided in order to prevent the diffusion of indium, i.e., of the thermal interfacial material into the material of the substrate, such as the silicon material and the like. In addition to these material layers, also one or more layers are provided so as to act as an adhesion layer appropriately attaching the thermal interfacial material to the back side metallization stack and thus to the semiconductor substrate. For this purpose, materials consisting of gold, gold alloys, platinum, gold/platinum alloys, copper, silver and the like are frequently used. Consequently, a moderately complex metallization layer stack is frequently to be formed on the back side or rear side of the semiconductor substrate, wherein a plurality of different materials have to be deposited, at least some of which may have a negative effect on the semiconductor devices and process techniques so that, in view of preventing any cross-contamination, the back side metallization is typically provided in a very advanced manufacturing stage. It turns out, however, that the presence of the back side metallization may still negatively affect the further processing, in particular in the context of complex metallization systems comprising a contact structure as a final part of the metallization system in order to directly connect to a package substrate, particularly during the process of dicing the semiconductor substrate so as to provide the individual semiconductor chips.
FIG. 1a schematically illustrates a top view of a semiconductor substrate 101 wherein a plurality of semiconductor devices 100 are formed above a front side 101F of the substrate 101. The semiconductor devices 100 in this manufacturing stage may be under-stood as die regions, i.e., portions of the substrate 101, in and above which one or more integrated circuit portions, possibly in combination with micro-mechanical, optical and other devices, are formed in accordance with a specified overall circuit layout. Thus, the semiconductor devices 100 may have a specific size and shape corresponding to the complexity of the one or more integrated circuit portions and other microstructural devices formed therein. As previously indicated, the semiconductor devices or dies 100 are provided in an array form on and above the front side 101F, wherein the number of semiconductor dies 100 that may be positioned on the substrate 101 depends on the overall size of the substrate 101, the size and shape of the semiconductor dies 100 and on the size of corresponding “frame” regions or scribe lines, which determine the lateral distance between any next neighbors of the semiconductor dies 100. For example, in the example shown in FIG. 1a, vertical frame regions or scribe lines, indicated by 102Y, are provided with substantially the same width as horizontal scribe lines 102X. It should be appreciated, however, that the width of the scribe lines 102X, 102Y may be different, as long as process-specific requirements are met by the scribe lines 102X, 102Y. For example, the width of these scribe lines has to at least take into consideration the space required for dicing, i.e., sawing, the substrate 101 into individual semiconductor chips, each of which may thus comprise a single one of the semiconductor devices 100. For example, the width of the scribe lines 102X, 102Y is selected so as to be greater than a thickness of a corresponding saw blade used for sawing the substrate 101 in an advanced manufacturing stage.
FIG. 1b schematically illustrates a cross-sectional view of the substrate 101 comprising the plurality of semiconductor dies 100. As illustrated, each of the semiconductor dies 100 may comprise a semiconductor layer 103 formed above or on the front side 101F of the substrate 101, wherein, in and above the semiconductor layer 103, a plurality of circuit elements 104, such as transistors, capacitors, resistors and the like, are provided in accordance with the overall layout of the one or more circuits provided in the semiconductor dies 100. For example, the circuit elements 104 may comprise circuit elements formed on the basis of critical dimensions of 50 nm and less in sophisticated applications. In other cases, significantly greater critical dimensions may be used when semiconductor devices of reduced packing density in the semiconductor layer 103 are considered. Furthermore, each of the semiconductor dies 100 comprises a contact level 105, which is to be understood as a dielectric material in combination with appropriate contact plugs or elements (not shown) so as to connect to the circuit elements 104 and also connect to a metallization system 110 formed above the contact level 105. The metallization system 110 typically comprises a plurality of metallization layers 111, 112, 113, 115, wherein the number of metallization layers depends on the overall complexity of the layout in and above the semiconductor layer 103, as is also previously discussed. In sophisticated applications, the metallization system 110 may comprise, at least in some critical metallization layers, sensitive dielectric materials, which may result in an inferior heat dissipation capability, as is also discussed above. Moreover, in some complex semiconductor devices, the metallization system 110 may comprise a contact structure 120, which is appropriately configured so as to allow a direct contact to a package substrate, which has formed thereon a “complementary” contact structure, for instance in the form of solder pads and the like, thereby allowing a direct connection of corresponding contact elements 121, such as solder balls, metal pillars and the like, with the package substrate. Consequently, in a correspondingly configured contact structure 120, substantially the entire surface area of each of the semiconductor dies 100 is available for providing contact elements 121 thereon, so that a large number of electrical connections to the periphery may be established, as is typically required in very complex semiconductor devices including complex control circuitry, such as CPUs, GPUs and the like. Depending on the required number of contact elements 121, the lateral pitch of the contact elements 121 is selected so as to comply with the electrical requirements. For example, the lateral size of the contact elements 121 may be on the order of magnitude of 200 μm and less, while a pitch thereof may also be on the same order of magnitude.
In other semiconductor devices, the contact structure 120 may have formed thereon appropriate bond pads (not shown), which are typically provided at the edge of the semiconductor dies 100 in order to enable a wire bonding contact regime after separating the individual semiconductor dies 100.
Furthermore, as discussed above, in sophisticated applications, the semiconductor dies 100 and thus the substrate 101 has formed on a back side or rear side 101B thereof a back side metallization 130, which typically comprises a plurality of individual metal-containing material layers, as discussed above. In this manner, an additional efficient path for heat dissipation is provided from the semiconductor layer 103 to the periphery via the substrate material 101 and the back side metallization 130.
The semiconductor dies 100 as illustrated in FIGS. 1a and 1b may be formed on the basis of any appropriate process strategy. That is, the circuit elements 104 are formed in and above the semiconductor layer 103 by any appropriate process technique, wherein also, in certain cases, circuit elements or portions thereof may be formed within the substrate material 101. Next, the contact level 105 is provided by depositing an appropriate dielectric material and forming conductive elements therein so as to connect to the circuit elements 104. Thereafter, the metallization layers 111, 112, 113, 115 are formed in accordance with any process strategy in order to obtain the desired electrical performance, for instance in terms of current drive capability, parasitic RC (resistance/capacitance) time constants and the like. Finally, the contact structure 120 is formed by providing appropriate solder bumps, metal pillars, bond pads and the like, depending on the complexity of the contact structure and generally of the devices 100 and depending on the desired contact technology to be used for attaching the semiconductor dies 100 to a package substrate or any other carrier material. As discussed above, in a very advanced manufacturing stage, the back side metallization 130 may be provided, for instance, by depositing a plurality of appropriate material layers, as described above. The devices 100 formed on the substrate 101 as shown in FIG. 1b may thus be in an appropriate manufacturing stage for separating the individual semiconductor dies 100.
FIG. 1c schematically illustrates the substrate 101 and the plurality of semiconductor dies 100 in a further advanced manufacturing stage. The separation of the plurality of semiconductor dies 100 is typically accomplished on the basis of a mechanical sawing process in which a diamond blade is used to cut through the substrate 101 and through the metallization system 110 and, if provided, through the back side metallization 130. Due to the increase of the substrate dimensions in order to increase the number of individual semiconductor dies 100 per substrate in view of superior productivity, however, also the thickness of the substrate 101 has to be appropriately adapted in view of mechanical stability and the like. For example, for a diameter of 200-300 mm, which is a frequently used standard in semiconductor facilities, the substrate 101 may have a thickness of approximately 700 μm and more. The scribe lines, for instance the scribe line 102Y as shown in FIG. 1c, is thus appropriately adapted in its width so as to allow a reliable cutting process on the basis of a diamond blade, wherein, however, a thickness thereof may not be arbitrarily reduced since in this case increased chippage may occur and thus reduce the overall production yield upon dicing substrates having the thickness of several hundred micrometers. Moreover, using a thin sawing blade would significantly reduce lifetime of the blade when sawing through the entire thickness of the substrate 101. Consequently, in conventional strategies, a two-step dicing process may typically be applied in which a sawing blade 105 of appropriate thickness is selected so as to cut into the substrate 101 and through the metallization system 110, i.e., the corresponding areas thereof corresponding to the scribe lines 102Y and 102X (FIG. 1a), thereby forming trenches 105F which extend into the depth of the substrate 101. For example, the trenches 105F may be formed so as to extend to approximately half the thickness of the substrate 101. To this end, a tape 140 is provided at the back side, i.e., the back side metallization 130, if provided, or the rear side 101B of the substrate 101.
FIG. 1d schematically illustrates the substrate 101 and the plurality of semiconductor dies 100 in a further advanced manufacturing stage. In this stage, a further sawing process is performed on the basis of a sawing blade 106 having a reduced thickness in order to form further trenches 106B through the previously provided wider trenches 105F. Consequently, the substrate 101 may be separated into individual semiconductor chips by using the sawing blade 106 and forming the trenches 106B, wherein the tape 140 still provides the required mechanical stability of the separated semiconductor chips.
FIG. 1e schematically illustrates a further advanced manufacturing stage. As illustrated, a plurality of individual semiconductor chips, which are also referred to with the reference sign 100, are provided after picking the separated devices from the tape 140 (FIG. 1d). In semiconductor chips such as the chip 100 in which the back side metallization 130 is provided, the cutting process may result in the creation of a certain amount of metal debris, which may migrate to the front side and finally to the metallization system 110.
FIG. 1f schematically illustrates a cross-sectional view of one of the semiconductor chips 100, wherein metal residues 131, created during the cutting through the back side metallization 130, may finally reach the metallization system 110 and thus the contact structure 120. In particular, since the closely spaced contact elements 121 are provided in the structure 120, the metal residues 131 may result in a high probability of creating short circuits, thereby contributing to significant yield losses during the further processing, i.e., during the connection of the semiconductor chip 100 to a package substrate.
Consequently, the conventional technique for separating semiconductor substrates into individual semiconductor chips requires scribe lines of appropriate width so as to comply with a required thickness of the sawing blade, while at the same time significant yield losses may be observed in complex semiconductor devices in which a back side metallization is to be provided. In this case, in some conventional approaches, it has been proposed to apply a back side patterning strategy in which the back side metallization may be patterned so as to obtain scribe lines in order to reduce the probability of creating metal debris. In this case, however, complex lithography and etch processes may have to be performed in a very advanced manufacturing stage at the rear side of the substrate, thereby significantly contributing to overall process complexity and thus production costs.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.